Principal Digital ASIC Design Engineer

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 1,800 employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com.

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Equal Employment Opportunity

Draper is committed to creating a diverse environment and is proud to be an affirmative action and equal opportunity employer. We understand the value of diversity and its impact on a high-performance culture. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, gender identity, national origin, veteran status, or genetic information.

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Draper Laboratory is seeking talented and motivated individuals to tackle challenging engineering problems. As a Principal Digital ASIC Designer, you will be responsible for designing high-performance digital ASICs in advanced technologies. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects in this area while leading and mentoring junior engineers.

The successful candidate will contribute to ASIC and FPGA development including architecture, analysis, design, and specification of ASICs and IP blocks. Candidate must have experience using high level design, simulation and verification tools and be familiar with process flows supporting design and verification for digital ASIC / FPGA efforts. Proficiency with ASIC and SoC design and development process flows is preferred. Preference will be given to candidates with an understanding of hardware security, signal or image processing, inertial instrument design, filter design and algorithm implementation in hardware.

Specific Responsibilities:

Requirements capture and derivation
• Architecture definition and performance analysis
• Integration of third-party IP
• Design implementation using SystemVerilog, Verilog or VHDL
• Familiarity with CDC, LEC and formal techniques
• Leading design and architecture teams
• Top-level chip integration

Required Qualifications:

• 15+ years of direct experience in the design of complex FPGAs and ASICs
• Strong analysis and problem solving skills
• Fluent in SystemVerilog/Verilog/VHDL
• Experience in Cadence or equivalent Digital ASIC Tool Suite, e.g., Genus, Innovus, Tempus, Voltus, etc.
• Experience with high-level design, simulation, and verification tools
• Experience with scripting languages Python/PERL and regular expressions
• Prior tapeouts or products released
• Ability to work onsite at Draper's Cambridge office as necessary.

Desired Qualifications:

• Familiarity with inertial instruments, control, signal or image processing.
• Familiarity with hardware security, e.g., encryption, key management, TRNG/DRNG, PUFs, root-of-trust, design obfuscation, etc.
• Familiarity with SOC tradespace including processor selection, memory and bus implementation and architecture
• Experience with Linux/UNIX OS, piping, batching, etc.
• Experience with emulation
• Active security clearance preferred

Security Requirement:

• Applicants selected for this position will be required to obtain and maintain a government security clearance.