ASIC Digital Design Engr, II

39483BR

USA - California - California, USA - California - Mountain View/Sunnyvale

Job Description and Requirements

Our Silicon IP business is all about integrating more capabilities into an SoC-faster. We offer the world's broadest portfolio of silicon IP-predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

At Synopsys, we're at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we're powering it all with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

CPU Design Engineer, Staff

This role is for the ARC Processor group at Synopsys and will be part of the architecture and design R&D Team. As a member of the ARC design Team you will gain understanding of the leading vision and neural network processors and contribute to architecting and designing state of the art DSP and control processor features of ARC processor cores, as well as understand and implement requirements of designing for Functional Safety. You will leverage your processor architecture and design skills for out of the box thinking to meet Power, Performance, Area requirements.

Primary Responsibilities Include

• Work with global design teams to develop and enhance ARC processors and related components
• Analyze requirements and develop architecture and micro-architecture specifications for portions of the design
• Collaborate with the modeling team to identify realistic use cases of application code, hardware benchmarks and analyze results
• Design and integrate processor modules using Verilog RTL code and develop test cases to check basic functionality
• Collaborate with the Verification team to support development of test plans to achieve functional coverage closure
• Analyze and optimize the design to achieve performance, speed, size, and power goals, working with the physical design teams
• Help design and implement Safety and Security Mechanisms for ARC Processor Cores
• Participate and Contribute to Functional Safety Audits
• As part of the largest EDA company, you will be in contact with remote teams on different continents and will work closely with customers located in Asia, Americas and Europe.

• Masters/Bachelor or above degree in electronic/electrical engineering or computer science
• 8+ years of ASIC/SoC design experience
• Experience with processor / DSP designs, memory hierarchies, cache controllers, arithmetic units
• Familiar with ARC or other Processer Cores
• Familiar with Industry standard interfaces like AMBA-AXI, AHB
• Proficient with Verilog RTL based logic design
• Proficient with design tools for simulation, synthesis and timing analysis
• Familiar with tools for Verilog linting, including CDC/MCP checks
• Familiar with programming in C and assembly for test cases
• Familiar with compilers and debug tools,
• Familiar with a scripting language for automation
• Exceptional debugging and troubleshooting skills
• Excellent communication skills, teamwork skills, autonomy
• Ability to work simultaneously on multiple tasks
• Has a proven desire to learn and explore new technologies. Demonstrates good research and problem-solving skills.
• Networks with senior internal and external personnel in own area of understanding.

The base salary range across the U.S. for this role is between $117,000 to $204,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Job Category

Engineering

Country

United States

Job Subcategory

ASIC Digital Design

Hire Type

Employee

Base Salary Range

$117,000 - $204,000